1. Field of the Invention
The invention relates to a delay circuit having at least two memory cells each comprising a capacitive memory element, a write transistor by means of which information to be delay be written from a write line into the capacitive memory element, and a read transistor by means of which information can be read from the capacitive memory element to a read line, and having a control arrangement which is clocked by means of a first control clock and whose input receives a control signal and which comprises intercoupled control circuits one of which is associated with a respective memory cell, each control circuit of the read transistor of the associated memory cell being controllable by means of the input signal and each control circuit of the write transistor of the associated memory cell being controllable by means of the output signal.
2. Description of the Related Art
Delay circuits of this type are known from EP 383 387, corresponding to U.S. Pat. No. 5,012,143. They are widely used in, inter alia, the video technique, for example, for realizing comb filters, for implementing noise reduction algorithms and for color decoding. These delay circuits have the characteristic feature that the output of a control circuit with the first clock simultaneously controls the write transistor of the memory cell associated with the control circuit and the read transistor of the subsequent memory cell. In the design of such delay circuits, particular attention should therefore be paid to the fact that no asymmetries due to different delay times of the control signal occur when the write and read transistors are controlled simultaneously.
In delay circuits which are realized as monolithically integrated circuits, the single memory cells are arranged in the same orientation on the silicon crystal, resulting in long, narrow rows. The number of memory cells which can be arranged on a silicon crystal can be increased by arranging a plurality of rows of memory cells on one silicon crystal. Such an arrangement is shown in FIG. 4 of EP 383 387. However, in this arrangement, the transistor from the last memory cell of a first row to the first memory cell of the subsequent row presents the problem that the delay times of the control signal for controlling the write transistor of the last memory cell of the first row and the read transistor of the first memory cell of the subsequent row are clearly different. This asymmetrical control of the write and read transistors leads to visible picture disturbances in the video technique. The same problem occurs, for example, when realizing a loop, in which the output of the control circuit of the last memory cell of a delay circuit of the type described in the preamble, is coupled to the input of the control arrangement of the delay circuit. The simultaneous control of the write transistor of the last memory cell and the read transistor of the first memory cell has hitherto been impossible.